The present invention disclosed herein relates to a Phase Locked Loop (PLL) circuit, and more particularly, to a PLL circuit which is driven with a differential controlled voltage.
PLL circuits which are used in wired/wireless communication, signal processing and data processing circuits are frequency feedback circuits that generate a signal having an arbitrary frequency in synchronization with a signal having a reference frequency which is inputted from the outside. The PLL circuits are configured for the frequency of an output signal to be controlled according to a phase difference between a reference signal and an output signal. In the PLL circuits, noise characteristics such as common mode noise and spur noise largely affect performances of analog and digital signal processing circuits. Therefore, research is actively being conducted on the decrease in noises of the PLL circuits.
PLL circuits that operate in a differential control scheme are being used for removing common mode noise. In typical differential controlled PLL circuits, however, spur noises occur due to the up-down current error of a charge pump and ripples that are generated in the control voltages of a Voltage Controlled Oscillator (VCO).